This invention relates to phase-locked loops.
The invention especially relates to phase-locked loops used for synthesizing RF channel frequencies in a transceiver, especially a transceiver used in WLAN (Wireless Local Area Network) applications. One application of the latter is in portable terminals such as lap-tops, point-of-sale terminals, which communicate with a host processor, and the transceiver may be accommodated in a standard PC expansion card such as a PCMCIA (Personal Computer Memory Card International Association)-sized card. This has a standard supply voltage of 3.0 volts .+-.10%, and the minimum supply voltage of 2.7 volts results in limitations in the implementation of the phase-locked loop.
Thus, in many conventional phase-locked loop synthesizers, a charge pump circuit is used to directly drive the voltage controlled oscillator (VCO), the loop filter components being connected from the charge pump circuit output to ground as shown in FIG. 1. The phase detector 1 provides either positive pulses from current source 2 or negative pulses from current source 3 to the voltage controlled oscillator 4, depending on whether the voltage controlled oscillator is at a higher or lower frequency than the reference oscillator. A bipolar charge pump using all NPN transistors for use with high frequency circuits has been proposed (GB-B-2 249 443), because PNP transistors are either not available or have poor performance. In this case, the charge pump circuit is followed by an operational amplifier to maintain the charge pump output at a constant voltage, and the operational amplifier output provides the VCO control voltage. When the VCO frequency range is wide, in the case of the low supply voltages referred to, it may be necessary to swing the amplifier output very close to the supply rails in order to obtain the necessary tuning range from the VCO.
A conventional operational amplifier will use a complementary output stage as shown in FIG. 2, but this will reduce the available swing at the output by at least twice the diode drop (equal to around 1.6 volts in total) which represents a considerable voltage in the case of a nominal 3 volts supply. An alternative output stage as shown in FIG. 3 uses complementary transistors in common emitter (rather than common collector as shown in FIG. 2) mode, and this reduces the voltage loss to only a few hundred millivolts if the output stage is properly designed. However, in the process, the output impedance is raised compared to FIG. 2, and this makes it difficult to restrain the charge pump output at the virtual earth input voltage of the operational amplifier.
In addition, if a charge pump circuit using all NPN transistors was employed in conjunction with an operational amplifier having the output stage shown in FIG. 3, this would be difficult to realise in practice, because the charge pump output current must be relatively high (pulses of at least .+-.1 milliamp duration 10 ns to 1 .mu.s at 1 MHz) for good noise performance, and this current would have to be sourced from the amplifier output under transient conditions if the loop settling time was not to be affected. In many high frequency processes, the size of the PNP transistor of the complementary pair shown in FIG. 3 needed to source 1 milliamp with reasonable gain would be excessive.